DC-Bus Capacitance Verification Method for an 800 V DC Data Center Considering Converter Closed-Loop Response Constraints

Existing DC-bus capacitance sizing methods generally treat load-power trajectories and converter dynamic responses separately, leaving no unified method that accounts for both. A closed-loop averaged model is developed that includes the voltage outer loop, load feedforward, inner-loop power tracking, and a source-side power slew-rate constraint. The effective closed-loop response time is defined, and the minimum capacitance is obtained through trajectory replay and bisection. Results show that the power-step method may underestimate the required capacitance because the result is jointly affected by the load-power trajectory and the source-side power slew-rate constraint. The proposed method extends power-step sizing to load-power-trajectory-based sizing considering closed-loop response, thereby supporting design comparison and parameter screening.