Abstract: This article aims to address the current situation of large workload, multiple participants, and tedious error positioning in the joint debugging of intelligent substation gateway machines control information. A virtual master station based intelligent substation gateway machines automatic acceptance system architecture is designed, and the principle and various functional modules of the automatic acceptance system are analyzed in depth. By deeply studying the correlation between different equipment protocols in the substation and relying on virtual master station simulation technology and IED simulation technology, the closed-loop signal verification circuit is achieved. At the same time, based on the analysis of the data received by the IEC61850 client and the virtual master station IEC104 client of the acceptance system, an innovative method for locating signal circuit configuration errors is proposed. This method can quickly locate devices that may have configuration errors during the process of intelligent station gateway machines acceptance. This solution eliminates manual nodes in the signal verification circuit, which is more efficient and accurate in verification results.