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计及变换器闭环响应约束的800 V直流数据中心母线电容量校核方法

DC-Bus Capacitance Verification Method for an 800 V DC Data Center Considering Converter Closed-Loop Response Constraints

  • 摘要: 现有母线电容量校核将负荷功率轨迹与变换器动态响应分开处理,尚缺少计及二者耦合作用的方法。构建含电压外环、负荷前馈、内环功率跟踪及源侧功率变化率约束的闭环平均值模型,定义等效闭环响应时间,采用轨迹回放和二分法确定最小电容量。结果表明,功率阶跃估算可能低估电容量需求,校核结果受负荷功率轨迹和源侧功率变化率约束共同影响。所提方法将功率阶跃校核扩展为计及闭环响应的负荷功率轨迹校核,可用于方案比较与参数筛选。

     

    Abstract: Existing DC-bus capacitance sizing methods generally treat load-power trajectories and converter dynamic responses separately, leaving no unified method that accounts for both. A closed-loop averaged model is developed that includes the voltage outer loop, load feedforward, inner-loop power tracking, and a source-side power slew-rate constraint. The effective closed-loop response time is defined, and the minimum capacitance is obtained through trajectory replay and bisection. Results show that the power-step method may underestimate the required capacitance because the result is jointly affected by the load-power trajectory and the source-side power slew-rate constraint. The proposed method extends power-step sizing to load-power-trajectory-based sizing considering closed-loop response, thereby supporting design comparison and parameter screening.

     

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